1. Field of the Invention
This invention relates to an interface circuit, and more particularly, to an interface circuit adaptable for information transmission between processors having different operating speeds.
2. Description of the Prior Art
Development of digital processing techniques and integrated circuit techniques has made it possible to fabricate a control circuit and/or a memory circuit on a semiconductor chip. The operation of a control circuit and/or a memory circuit formed on a single chip is controlled by clock pulses. A data processing system includes a plurality of chips coupled to each other by signal buses through which information is transferred. When a plurality of chips are coupled by the signal bus, timing control of the data transmission between the chips is required. Here, if all the chips coupled by the bus are controlled by a common clock pulse, the frequency of the timing pulse must be equal to the operating frequency of the chip having the lowest operating speed. Thus, the throughput of the system drops down and high speed processing can not be expected. It is not possible, on the other hand, to use the clock pulse of the chip having the highest operating speed as the timing pulse for information transmission. In order to obtain a system having a high throughput, each chip must be individually subjected to separate timing control. In this case, however, interfacing the chips becomes difficult for an interface circuit must then be disposed between chips having different operating speeds. Such an interface must be made so as not to interfere operation of the chips.
With the background described above, an interface circuit using a first-in-first-out memory (hereinafter referred to as the "FIFO memory") has been widely used. The FIFO memory is constructed in such a manner that data are read out in the sequence in which they are written. A read operation and a write operation of the data are controlled by addressing means. Therefore, the timing of data input and data output during data transmission can be controlled relatively freely. However, another problem occurs in that the hardware circuit for the address control becomes very complicated. More specifically, the memory requires an address generation circuit, an address decoder circuit, a read pointer, a write pointer and a circuit for designating the memory location in which data is stored.
A FIFO memory having a simplified address control circuit is disclosed in U.S. Pat. No. 4,459,681 which issued on July 10, 1984 and assigned to the same Assignee of this Application. It consists of a memory section and a control section but does not need an address generation circuit, an address decoder, a write pointer and a read pointer. Accordingly, this prior art circuit provides the advantage that the size of the interface circuit can be reduced. On the other hand, the control section of the FIFO memory of this prior art circuit requires a plurality of delay type flip-flops (D-F.F). The states of these flip-flops are changed by read/write control signals, and transferred data are written from the output stage of the memory section and transferred to a receiver in accordance with the states of the D-F.Fs.
However, this FIFO memory needs, in addition to a control section, a memory section into which data is written. It it is conceivable, in principle, to use a shift register in place of the memory section. The size of the shift register is smaller than that of the memory section. However, when using the shift register synchronization of the transmitting chip with the receiving chip is extremely difficult because the shift speed is different from the operating speeds of both the transmitter and the receiver.
A data processing chip (a pipeline processor) having pipeline processing circuits will be considered as an example of a data receiving chip. The pipeline processor includes a plurality of pipeline stages coupled in series, with each stage being separated by a pipeline latch circuit. Thus, each stage can be operated in parallel in a predetermined pipeline cycle. Data derived from a transmitter is applied to a first stage in response to a pipeline clock and is sequentially shifted to the subsequent stages during each pipeline cycle. The data thus shifted is processed at each stage as the occasion arises with the result being taken out from the output stage.
The maximum processing capacity of the pipeline is realized when data to be processed are applied to all the pipeline stages. In practice, however, effective data to be processed do not always exist at all the stages. Accordingly, whenever no data appears at a data input, a NOP (no operation) cycle occurs at each stage. To effectively use the pipeline, therefore, it is desirable to apply the data, to be applied to the pipeline, as continuously as possible. A pipeline cycle is determined by the processing instructions at the pipeline stage and is limited by the hardware circuit used. In order to apply the data in every pipeline cycle, as continuously as possible, a device operable at a high speed equal to or higher than the pipeline speed should be provided as a transmitter. Ideally, a transmitting device should operate in synchronism with the pipeline cycle but such operation is very difficult to realize in practice. Even if data to be applied to the pipeline is produced in a cycle shorter than the pipeline cycle, missmatching will occur in an interface unless it is out of synchronism with the pipeline cycle. For example, the data, which is generated immediately after the pipeline cycle, can not be applied to a first pipeline stage at that timing even though data does not exist at the first pipeline stage. As a result, the data to be processed must be held until the next pipeline cycle. In such a case, an empty cycle always occurs in the pipeline cycle and hence, the processing speed efficiency drops.
This shortcoming occurs not only in an interface between chips but also in an interface between a processor unit and a peripheral unit such as a keyboard unit, a printer unit and a display unit. Moreover, even if an interface circuit is built in either a transmitting section or a receiving section, the shortcoming can not be omitted. Further, even if a common system clock is used as the basic clock for each unit, when the operating speed (for example, data input/output speed) of each unit is different from each other, the shortcoming described above may also occur.
As described above, in a processor to which a plurality of data sets to be processed are transferred in series, an interface circuit is particularly important. Particularly, in a system wherein a master processor operating at high speed and slave controllers (e.g., keyboard controllers, printer controllers, display controllers, etc.) operating at low speeds are included, an interface circuit is necessarily required. The interface circuit may be either disposed between a master side and a slave side or be incorporated in the master side or the slave side. Especially in the latter case, the interface circuit in a device or on a chip is preferably as small as possible. Further, the interface circuit is also required for a device whose high speed circuit portion and low speed circuit portion are formed on the same chip.